1. Field of the Invention
The present invention relates to a shift register, a shift register array, and a display apparatus; in particular, the invention relates to a shift register, a shift register array, and a display apparatus, which utilize input signals, output signals, and clock signals to decrease the stress, resulted from having a bias for a long time, of the transistors thereof.
2. Descriptions of the Related Art
Gate drivers and source drivers are disposed out of panels of most of the liquid crystal displays, and are configured to generate gate pulse signals and data signals. However, this way would cost much so other ways are developed. For example, manufacturing a gate driver, comprising shift registers, on a glass substrate is a so-called integrated driving circuit.
An amorphous thin film transistor process is often used for an active matrix liquid crystal display (AMLCD) in the present days. There are many disadvantages when shift registers are disposed on a glass substrate under this process. For example, the panel would operate abnormally because one or some of the shift registers are biased for a long time when the panel is lighted up.
U.S. Patent Publication No. 2004/0046729 discloses a shift register 1, as shown in FIG. 1. It has the above-mentioned defect. Firstly, in addition to driving a transistor 104, configured to be pull-up, node B further drives a transistor 102 and a transistor 103. The node B is overloaded, so an output signal of the shift register 1 is delayed. Furthermore, a transistor 101 and the transistor 102 need to have a size ratio larger than 1:16 for a better efficiency at node A. As a matter of result, VGS of the transistor 101 is equal to about VON−VOFF. This high cross voltage increases the current flowing through the transistor 101, and the node A generates a bias for a long time. Besides, the transistor 101 also has a bias for a long time because the voltage of node E is larger than 0V. The aforementioned defects cause that the panel, which uses this shift register 1, is unable to operate normally over a long period of time.
FIG. 2 is an ideal timing diagram of the shift register in FIG. 1. CKV denotes a positive clock; CKVB denotes a negative clock; GOUT[N−1], GOUT[N], and GOUT[N+1] denotes output signals of shift registers in different stages. N−1 is a previous stage of N, N is a previous stage of N+1, and N is the shift register shown in FIG. 1. Signal C denotes an ideal waveform at the node B in FIG. 1. The signal C is formed by CKV, GOUT[N−1], and GOUT[N]. The aforementioned defect leads to distortion of the signal C, and the lifetime of the shift register would be, therefore, reduced.
If amorphous silicon is adopted as the material of a liquid crystal display (LCD) panel, the bias defect suffered by the transistor should be taken into consideration more seriously so that the design of the shift register can ensure an operating time of the LCD panel would not be affected. U.S. Patent Publication No. 2004/0165692 discloses a shift register 3 shown in FIG. 3; this shift register 3 cannot overcome this defect yet. In this patent, a transistor 301 suffers an over bias and the lifetime of the transistor 301 is reduced thereby due to a high voltage of node D. Accordingly, the lifetime of the shift register and the panel is reduced, too.
Accordingly, the current circuitry of shift registers suffers an over bias. This not only delays an output, but also reduces the lifetime of the panel. Therefore, a solution to reducing the bias suffered by any transistor of the shift register is urgently required in this industrial field.